Shri Mata Vaishno Devi University
Official Website     Last Updated: 12th Apr, 2024
Admission 2024-25
Shri Mata Vaishno Devi University
Official Website     Last Updated: 12th Apr, 2024
Admission 2024-25

SMVDU’s Puja Singh Unveils Innovative Harmonic Minimization Technique at IEEE CICN 2023 in Bangkok

Ms. Puja Singh, a fourth-year B.Tech student at the School of Electrical Engineering, Shri Mata Vaishno Devi University, achieved a significant milestone by publishing her research paper at the 15th IEEE International Conference on “Computer Intelligence and Communication Networks (CICN 2023),” held in Bangkok, Thailand, on December 22nd – 23rd, 2023. The conference served as a dynamic platform for bridging the gap between theoretical knowledge and practical applications, fostering a vibrant exchange of cutting-edge developments. It brought together researchers and industry experts from various domains. Ms. Singh’s paper, titled “Harmonic Minimization of Multilevel Inverter Using Bat Algorithm,” focuses on a seven-level single-phase cascaded H-Bridge multilevel inverter, utilizing the BAT Algorithm for optimization. The selection of the BAT Algorithm was driven by its proven ability to provide high-quality solutions, stable convergence characteristics, and efficient computational performance. Drawing inspiration from bat echolocation, the Bat Algorithm effectively addresses complex power system optimization challenges, resulting in minimized Total Harmonic Distortion and the provision of a robust and high-quality power supply.

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